1. Field of the Invention
The present invention relates to a memory chip array, and more particularly, to a memory chip array with optimized arrangement by forming a predecoder commonly connected to memory arrays on a region of a memory chip array.
2. Description of the Related Art
As industries and multimedia field develop, a demand for large-capacity information devices being used in computers or telecommunication apparatus is gradually increasing. Due to such a demand, information devices having high integration are being researched and developed.
Semiconductor memory devices have been reducing the size of elements and continuously maximizing the portion integration within a plane given through attempts such as making in a three-dimensional structure. Recently, the size of a portion element has been reduced down to tens of nanometers, and thus the industry faces a great challenge in terms of miniaturizing portion elements.
FIG. 1A is a plan view illustrating a memory chip structure according to prior art. Referring to FIG. 1A, for example, a row decoder 13 including a predecoder 11 and a row select 12 are formed on a first side of a memory cell array 10, and a sense amplifier and a column decoder 14 are formed on a second side of the memory cell array 10. The row decoder 13 and the column decoder 14 are formed individually at every cell array in the memory chip array. The memory chip having such a structure may be formed by, for example, fabricating the row decoder 13, the column decoder 14, and a sense amplifier and the like on a silicon surface, and fabricating a cell array thereon. Recently, a stackable memory structure with a three-dimensional configuration has been introduced. As shown in FIG. 1B, a row decoder R and a column decoder C were arranged on a silicon surface in an alternating manner, and a memory array A was arranged thereon. Such a checkerboard patterned arrangement is known as an arrangement that efficiently utilizes a silicon area.
Such prior art includes several problems. First, referring to FIG. 1B, the edges of memory cells have reduced utilization due to the fabrication of the row decoders R and the column decoders C with half a block size. Second, referring to FIG. 1A, each row decoder 13 is divided into multiple decoders, and among the multiple decoders, the predecoder 11 is located between the cell arrays 10. By having the predecoder 11 for every cell array 10, the overall area of the memory chip array is increased. In order to overcome such problems, a method has been introduced, wherein only the row decoder 13 is formed below the memory cell array, and the sense amplifier and the column decoder 14 are arranged between the cell array blocks or the like. In this case, however, the area of the sense amplifier and the column decoder 14 are significantly large, and thus the overall area of the memory chip array may become larger. Moreover, only a single layered active circuit plane can be formed, and thus forming a multi-layered memory array is limited.